Add selecting network circuit #621
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tilk
approved these changes
Mar 21, 2024
lekcyjna123
approved these changes
Mar 24, 2024
| merged = Array(Signal(self.layout) for _ in range(total_len)) | ||
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| for i in range(len(a)): | ||
| m.d.comb += merged[i].eq(Mux(cnt_a <= i, b[i - cnt_a], a[i])) |
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This generates a lot of subtractors. Why you doesn't use shifts?
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I don't think it is a problem. These are not proper substractions. In fact, the synthesis tool can permutate inputs of the mux and simply address it using cnt_a.
Shifting by variable number of bits in particular won't be better than a mux.
whitequark
reviewed
Apr 9, 2024
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| @parameterized_class( | ||
| ("n"), |
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Thanks for pointing this out - it should. However, apparently this decorator correctly handles this case:
if isinstance(attrs, string_types):
attrs = [attrs]
tilk
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Nov 25, 2024
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I didn't call it sorting network, because in fact it doesn't sort -- we don't care about items that are not valid. We only select valid inputs and group them together.
The generated circuit looks nice (n=6):
https://digitaljs.tilk.eu/#2cde77f56b8cfd56a81defc25c4adc6257fc3f60f78f301a38ddc4a7d7330310